1. Field of Invention
The present invention relates to a semiconductor device and the method for manufacturing and operating the same, and more particularly to a memory device and the method for manufacturing and operating the same.
2. Description of Related Art
Non-volatile memory is a kind of memory device that the data stored therein will not be lost when the power supply is cut off, which includes such non-volatile memories that data programming, reading, and erasing operations can be performed thereto repeatedly, for example, “Electrically Erasable Programmable Read-Only Memory” (EEPROM) and “silicon Nitride Read-Only Memory”, and such non-volatile memories have been applied widely into various personal computers and electronic devices.
FIG. 1A is a top view of a conventional Nitride Read-Only Memory. FIG. 1B is a cross-sectional view of the cut along line I-I′ of FIG. 1A. Referring to FIGS. 1A and 1B, to manufacture this Nitride Read-Only Memory, a plurality of gate structures 125 are formed on the substrate 100 first, wherein a gate structure 125 includes, from bottom to top, an ONO (oxide/nitride/oxide) stack layer 110 and a gate 120. Then, buried bit lines 130 are formed, and a silicon oxide layer 140 is formed at two sides of the gate structures 125. After that, the word lines 150 are formed on the gate structures 125 to connect the gate structures 125 in series.
In the foregoing manufacturing process of Nitride Read-Only Memory, while the silicon oxide layer 140 is formed, the silicon oxide on the gates 120 is removed through chemical mechanical polishing (CMP). Or, silicon nitride is formed on the gates 120 first, and then the silicon oxide on the gates 120 is removed through lift-off. These methods will either cause defects in the memory device, or have complex procedure, so that they are very disadvantageous in the manufacturing process.
Besides, since the gates 120 become block structures from the original stripe structures while the word lines 150 are formed, thus bridging and short circuit will be caused between the word lines 150 if the etching of the gates 120 is incomplete.
Moreover, integrated circuit technology is developing quickly; accordingly the expectation to the device integrity is getting higher and higher. Thus, the affection of short channel effect will get more obvious along with the reduction of line widths. To prevent short channel effect, the depth of the buried bit lines 130 has to be decreased as much as possible. However, this will cause the resistance values of the buried bit lines 130 being too high, which is very disadvantageous to the performance of the memory device.
An EEPROM is disclosed in the U.S. Pat. No. 5,284,785, wherein no doped region is formed in the substrate, so that the short channel effect can be reduced, and the operating area thereof is wide. Moreover, it's not necessary to dispose a field oxide.
However, a floating gate and a controlling gate have to be formed in this EEPROM, so it is difficult to integrate this EEPROM with a general CMOS process, and a silicon oxide layer has to be disposed additionally to separate the floating gate and the bit lines. Besides, an n-type lightly doped region has to be formed additionally in the memory device to improve the operating efficiency of FN tunneling.